| Principal Engineer, Reliability Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
In this high-impact leadership role, you will be the primary architect of the reliability roadmap spanning our silicon photonics platform and the mixed-signal EICs that drive it. You will bridge the gap between R&D and high-volume manufacturing, ensuring that our optical I/O solutions — PIC and EIC together — exceed the stringent requirements of the world’s leading AI and data center customers. Your expertise will directly influence chiplet co-design, foundry process qualification, and system-level reliability at the PIC-EIC interface.
Key Responsibilities - Product Qualification & Corrective Action follow up
- Own the execution and plan for the production qualification products, which includes silicon photonics and mixed-signal EIC components. Complying with JEDEC, Telcordia (GR-468), and MIL-STD standards..
- Develop corrective action plans (CAPA) to resolve reliability issues discovered during qualification or in-field deployment, partnering with failure analysis, operation and design teams as needed.
- Design for Reliability (DfR) — PIC and EIC
- Integrate DfR principles into the earliest stages of the product development lifecycle (NPI) for both the photonics chiplet and its mixed-signal EIC.
- Conduct Failure Mode and Effects Analysis (FMEA) across the PIC-EIC system, covering optical elements (waveguides, ring resonators, modulators, photodetectors) and mixed-signal circuit blocks (drivers, TIAs, ADC/DAC, control loops).
- Collaborate with photonics design, analog/mixed-signal IC design, and layout teams to implement design-based mitigations for known failure mechanisms, including electromigration, dielectric breakdown, hot-carrier injection, NBTI/PBTI, and optical degradation.
- Define reliability guardbands and design rules at the PIC-EIC interface (co-packaged optics), where electrical and optical degradation modes interact.
- Foundry & Ecosystem Reliability
- Serve as the technical lead for reliability with foundry partners across both silicon photonics and CMOS/mixed-signal process nodes, ensuring their processes meet Ayar Labs’ quality benchmarks.
- Define and drive wafer-level reliability (WLR) structures and test vehicles to characterize new photonics and mixed-signal EIC process nodes.
- Manage reliability requirements for advanced packaging and Co-Packaged Optics (CPO) with OSAT partners, covering both optical and electrical interconnects.
- Advanced Reliability Modeling
- Develop and refine Physics-of-Failure (PoF) models for silicon photonics devices and mixed-signal EIC circuits to predict FIT (Failures in Time) rates and DPPM.
- Utilize statistical software (JMP, Minitab, or Python) to perform Weibull and Lognormal analysis on accelerated life testing (ALT) and degradation data for both PIC and EIC populations.
- Model the impact of environmental stressors — thermal cycling, humidity, high-power optical loads, and electrical stress — on the long-term performance of the combined photonics-EIC system.
- Build unified reliability degradation and margin models that capture the interaction between optical link margin and EIC circuit aging.
Required Qualifications - Education: Bachelor’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
- Experience: 10+ years of semiconductor reliability experience, with at least 5 years focused specifically on Silicon Photonics and/or Mixed-Signal EIC reliability.
- Mixed-Signal: Working knowledge of mixed-signal IC design and the reliability mechanisms unique to it (electromigration, HCI, NBTI/PBTI, ESD, latch-up) in addition to photonics-specific mechanisms.
- Foundry Knowledge: Deep understanding of foundry process flows and the reliability challenges unique to photonics and CMOS/mixed-signal processes, including optical power handling, aging, and thermal management in CPO.
- Modeling Mastery: Proven track record developing aging models (Arrhenius, Coffin-Manson, etc.) for semiconductor and photonic devices.
- Standards Expertise: Familiarity with JEDEC, Telcordia (GR-468), and MIL-STD qualification standard and the Physics behind these requirements
- Computer skills: Proficiency in using Phyton to control lab equipment and DUT
Preferred Qualifications - Education: PhD or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
- PhD degree with 15+ years of relevant experience
- Hands-on experience with Python for automated reliability data pipelines.
- Prior experience co-qualifying an optical chiplet alongside its companion EIC in a co-packaged optics (CPO) architecture.
- Demonstrated leadership experienceExperience in reliability issues with advanced silicon technologies (7
- 3nm), advanced packaging (CPO/COWOS) and FAU reliability
- Direct external customer interaction experience
Salary range: $200,000 - $260,000 NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
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