ASIC Design Engineer at Ayar Labs
Santa Clara, CA, US
ASIC Design Engineer
The ASIC Engineer is responsible for design, integration, and verification of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team, covering roles from custom circuit design to optical device design. Each team member is expected to contribute across a broad range of tasks and to gain new skillsets to grow with the company. The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Develop and optimize RTL designs for use in complex digital systems
Develop verification methodology and testbenches for digital and mixed-signal blocks
Design and contribute to design for test (DFT) methodologies
Contribute to automated design methodologies for ASIC physical design
Perform ASIC physical design (synthesis, place-and-route), and sign-off (DRC/LVS) of mixed-signal SoCs
Work with designers to integrate custom blocks into a digital toolflow
MS in Electrical Engineering, Computer Engineering or relevant fields with 3+ years of chip design industry experience
PhD in Electrical Engineering, Computer Engineering or relevant fields focused on chip-level digital design (RTL and physical design)
History of assuming responsibility for a variety of technical tasks and completing projects independently
Proficient in Verilog for both RTL design and verification
Proficient in ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), verification (NCSIM, VCS, ModelSim), and sign-off (DRC, LVS) tools
Proficient in writing timing constraints and deep understanding of timing analysis
Proficient in scripting or programming languages
THE IDEAL CANDIDATE WILL ALSO HAVE:
Experience designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
Experience working on digital designs with multiple clock domains and clock dividers
Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
Working knowledge of the Cadence Virtuoso design environment for manual schematic entry, layout, and simulation
Performed silicon bring-up, debug, and evaluation
Programming experience in Python
Knowledge of high-speed SerDes or SerDes components
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ABOUT AYAR LABS
At Ayar Labs we are lighting up electronics for a brighter future. With our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with brilliant people on challenging, paradigm-shifting work. Our optical I/O technology removes the bottlenecks created by today’s electrical I/O, making it possible to continue the computing system performance scaling that Moore’s Law enabled until now. We have a commitment to win big in the marketplace based on the strengths of our technology, and we approach everything with an eye to massive scalability. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to achieve big wins, leveraging our patent portfolio which promises products that deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. We offer a comprehensive benefits plan designed to keep our team healthy and happy.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.